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Low Power Audio Codec SSM2602
FEATURES
Stereo, 24-bit analog-to-digital and digital-to-analog converters DAC SNR: 100 dB (A-weighted), THD: -80 dB at 48 kHz, 3.3 V ADC SNR: 90 dB (A-weighted), THD: -80 dB at 48 kHz, 3.3 V Highly efficient headphone amplifier Stereo line input and monaural microphone input Low power 7 mW stereo playback (1.8 V/1.5 V supplies) 14 mW record and playback (1.8 V/1.5 V supplies) Low supply voltages Analog: 1.8 V to 3.6 V Digital core: 1.5 V to 3.6 V Digital I/O: 1.8 V to 3.6 V 256/384 oversampling rate in normal mode; 250/272 oversampling rate in USB mode Audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz 28-lead, 5 mm x 5 mm LFCSP (QFN) package
GENERAL DESCRIPTION
The SSM2602 is a low power, high quality stereo audio codec for portable digital audio applications with one set of stereo programmable gain amplifier (PGA) line inputs and one monaural microphone input. It features two 24-bit analog-todigital converter (ADC) channels and two 24-bit digital-toanalog (DAC) converter channels. The SSM2602 can operate as a master or a slave. It supports various master clock frequencies, including 12 MHz or 24 MHz for USB devices; standard 256 fS or 384 fS based rates, such as 12.288 MHz and 24.576 MHz; and many common audio sampling rates, such as 96 kHz, 88.2 kHz, 48 kHz, 44.1 kHz, 32 kHz, 24 kHz, 22.05 kHz, 16 kHz, 12 kHz, 11.025 kHz, and 8 kHz. The SSM2602 can operate at power supplies as low as 1.8 V for the analog circuitry and as low as 1.5 V for the digital circuitry. The maximum voltage supply is 3.6 V for all supplies. The SSM2602 software-programmable stereo output options provide the user with many application possibilities because the device can be used as a headphone driver or as a speaker driver. Its volume control functions provide a large range of gain control of the audio signal. The SSM2602 is specified over the industrial temperature range of -40C to +85C. It is available in a 28-lead, 5 mm x 5 mm lead frame chip scale package (LFCSP).
APPLICATIONS
Mobile phones MP3 players Portable gaming Portable electronics Educational toys
AVDD MICBIAS
-34.5dB TO +33dB, 1.5dB STEP
FUNCTIONAL BLOCK DIAGRAM
VMID AGND DBVDD DGND DCVDD HPVDD PGND
SSM2602
BYPASS SIDETONE
6dB TO 15dB/MUTE 3dB STEP -73dB TO +6dB, 1dB STEP
RHPOUT RLINEIN MUX ADC DAC ROUT MICIN
0dB/20dB/ 40dB BOOST
DIGITAL PROCESSOR LOUT MUX ADC DAC LHPOUT
-34.5dB TO +33dB, 1.5dB STEP
LLINEIN
6dB TO 15dB/MUTE 3dB STEP -73dB TO +6dB, 1dB STEP
SIDETONE BYPASS
CLK
DIGITAL AUDIO INTERFACE
CONTROL INTERFACE
MCLK/ XTO CLKOUT XTI
PBDAT RECDAT BCLK PBLRC RECLRC MODE CSB
SDIN SCLK
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
06858-001
SSM2602 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Digital Filter Characteristics ....................................................... 4 Timing Characteristics ................................................................ 5 Absolute Maximum Ratings............................................................ 8 Thermal Resistance ...................................................................... 8 ESD Caution.................................................................................. 8 Pin Configuration and Function Descriptions............................. 9 Typical Performance Characteristics ........................................... 10 Converter Filter Response......................................................... 10 Digital De-Emphasis .................................................................. 11 Theory of Operation ...................................................................... 12 Digital Core ................................................................................. 12 ADC and DAC............................................................................ 12 ADC High Pass and DAC De-Emphasis Filters ..................... 12 Automatic Level Control (ALC)............................................... 13 Analog Interface ......................................................................... 14 Digital Audio Interface .............................................................. 16 Software Control Interface........................................................ 18 Typical Application Circuits ......................................................... 19 Register Map ................................................................................... 20 Register Map Details ...................................................................... 21 Left-Channel ADC Input Volume, Address 0x00.................. 21 Right-Channel ADC Input Volume, Address 0x01 ............... 22 Left-Channel DAC Volume, Address 0x02............................. 23 Right-Channel DAC Volume, Address 0x03 .......................... 23 Analog Audio Path, Address 0x04 ........................................... 24 Digital Audio Path Control, Address 0x05 ............................. 24 Power Management, Address 0x06.......................................... 25 Digital Audio I/F, Address 0x07 ............................................... 26 Sampling Rate, Address 0x08.................................................... 26 Active, Address 0x09.................................................................. 29 Reset, Address 0x0F ................................................................... 29 ALC Control 1, Address 0x10................................................... 30 ALC Control 2, Address 0x11................................................... 30 Noise Gate, Address 0x12.......................................................... 31 Outline Dimensions ....................................................................... 32 Ordering Guide .......................................................................... 32
REVISION HISTORY
2/08--Revision 0: Initial Version
Rev. 0 | Page 2 of 32
SSM2602 SPECIFICATIONS
TA = 25C, AVDD = DVDD = 3.3 V, PVDD = 3.3 V, 1 kHz signal, fS = 48 kHz, PGA gain = 0 dB, 24-bit audio data, unless otherwise noted. Table 1.
Parameter RECOMMENDED OPERATING CONDITIONS Analog Voltage Supply (AVDD) Digital Power Supply Ground (AGND, PGND, DGND) POWER CONSUMPTION Power-Up Stereo Record (1.5 V and 1.8 V) Stereo Record (3.3 V) Stereo Playback (1.5 V and 1.8 V) Stereo Playback (3.3 V) Power-Down LINE INPUT Input Signal Level (0 dB) Input Impedance Min 1.8 1.5 Typ 3.3 3.3 0 Max 3.6 3.6 Unit V V V Conditions
7 22 7 22 40 1 x AVDD/3.3 200 10 480 10 90 84 -80 -75 80 0 1.5 -80 1 85 -70 50 80 10 10 0.75 x AVDD 3 40
mW mW mW mW W V rms k k k pF dB dB dB dB dB dB dB dB V rms dB dB dB dB k pF V mA nV/Hz
PGA gain = 0 dB PGA gain = +33 dB PGA gain = -34.5 dB PGA gain = 0 dB, AVDD = 3.3 V PGA gain = 0 dB, AVDD = 1.8 V -1 dBFS input, AVDD = 3.3 V -1 dBFS input, AVDD = 1.8 V
Input Capacitance Signal-to-Noise Ratio (A-Weighted) Total Harmonic Distortion (THD) Channel Separation Programmable Gain Gain Step Mute Attenuation MICROPHONE INPUT Input Signal Level Signal-to-Noise Ratio (A-Weighted) Total Harmonic Distortion Power Supply Rejection Ratio Mute Attenuation Input Resistance Input Capacitance MICROPHONE BIAS Bias Voltage Bias Current Source Noise in the Signal Bandwidth LINE OUTPUT DAC Full-Scale Output Signal-to-Noise Ratio (A-Weighted) THD + N Power Supply Rejection Ratio Channel Separation
70
-34.5
+33.5
Microphone gain = 0 dB (RSOURCE = 40 k) 0 dBFS input, 0 dB gain
20 Hz to 20 kHz -1 dBFS input DAC + line output
85
1 x AVDD/3.3 100 94 -80 -75 50 80
V rms dB -70 dB dB dB
AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V
Rev. 0 | Page 3 of 32
SSM2602
Parameter HEADPHONE OUTPUT Full-Scale Output Voltage Maximum Output Power Signal-to-Noise Ratio (A-Weighted) THD + N Power Supply Rejection Ratio Mute Attenuation LINE INPUT TO LINE OUTPUT Full-Scale Output Voltage Signal-to-Noise Ratio (A-Weighted) Total Harmonic Distortion Power Supply Rejection MICROPHONE INPUT TO HEADPHONE OUTPUT Full-Scale Output Voltage Signal-to-Noise Ratio (A-Weighted) Power Supply Rejection Ratio Programmable Attenuation Gain Step Mute Attenuation Min Typ 1 x AVDD/3.3 30 60 96 90 -65 -60 50 80 1 x AVDD/3.3 92 86 -80 -80 50 Max Unit V rms mW mW dB dB dB dB dB V rms dB dB dB Conditions
85
RL = 32 RL = 16 AVDD = 3.3 V AVDD = 1.8 V POUT = 10 mW POUT = 20 mW
AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V
1 x AVDD/3.3 94 88 50 6 3 80 15
V rms dB dB dB dB dB
AVDD = 3.3 V AVDD = 1.8 V
DIGITAL FILTER CHARACTERISTICS
Table 2.
Parameter ADC FILTER Pass Band Pass-Band Ripple Stop Band Stop-Band Attenuation High-Pass Filter Corner Frequency Min 0 0.5 fS 0.04 0.555 fS -61 3.7 10.4 21.6 0 0.5 fS Pass-Band Ripple Stop Band Stop-Band Attenuation Core Clock Tolerance Frequency Range Jitter Tolerance 0.04 0.555 fS -61 8.0 50 13.8 0.445 fS Typ Max 0.445 fS Unit Hz Hz dB Hz dB Hz Hz Hz Hz Hz dB Hz dB MHz ps Conditions 0.04 dB -6 dB
f > 0.567 fS -3 dB -0.5 dB -0.1 dB 0.04 dB -6 dB
DAC FILTER Pass Band
f > 0.565 fS
Rev. 0 | Page 4 of 32
SSM2602
TIMING CHARACTERISTICS
Table 3. I2C(R) Timing
Parameter tSCS tSCH tPH tPL fSCLK tDS tDH tRT tFT tHCS tMIN 600 600 600 1.3 0 100 Limit tMAX Unit ns ns ns s kHz ns ns ns ns ns
tSCH tPL
SCLK
526 900 300 300
600
Description Start condition setup time Start condition hold time SCLK pulse width high SCLK pulse width low SCLK frequency Data setup time Data hold time SDIN and SCLK rise time SDIN and SCLK fall time Stop condition setup time
tHCS tDS tPH tDH tFT tSCS
06858-036
SDIN
tRT
Figure 2. I2C Timing
Table 4. SPI Timing
Parameter tDSU tDHO tSCH tSCL tSCS tCSS tCSH tCSL tPS tMIN 20 20 20 20 60 20 20 20 0 Limit tMAX Unit ns ns ns ns ns ns ns ns ns
tCSL tSCH tSCL
SCLK
5
Description SDIN to SCLK setup time SCLK to SDIN hold time SCLK pulse width high SCLK pulse width low SCLK rising edge to CSB rising edge CSB rising to SCLK rising CSB pulse width high CSB pulse width low Pulse width of spikes to be suppressed
tCSH
CSB
tSCS
tCSS
tDSU
SDIN
tDHO
Figure 3. SPI Timing
Rev. 0 | Page 5 of 32
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SSM2602
Table 5. Digital Audio Interface Slave Mode Timing
Parameter tDS tDH tLRSU tLRH tDD tBCH tBCL tBCY tMIN 10 10 10 10 Limit tMAX Unit ns ns ns ns ns ns ns ns
tBCH
BCLK PBLRC/ RECLRC
30 25 25 50
Description PBDAT setup time from BCLK rising edge PBDAT hold time from BCLK rising edge RECLRC/PBLRC setup time to BCLK rising edge RECLRC/PBLRC hold time to BCLK rising edge RECDAT propagation delay from BCLK falling edge (external load of 70 pF) BCLK pulse width high BCLK pulse width low BCLK cycle time
tBCL
tBCY
tDS tLRH
PBDAT
tLRSU tDH
RECDAT
Figure 4. Digital Audio Interface Slave Mode Timing
Table 6. Digital Audio Interface Master Mode Timing
Parameter tDST tDHT tDL tDDA tBCLKR tBCLKF tBCLKDS tMIN 30 10 Limit tMAX Unit ns ns ns ns ns ns Description PBDAT setup time to BCLK rising edge PBDAT hold time to BCLK rising edge RECLRC/PBLRC propagation delay from BCLK falling edge RECDAT propagation delay from BCLK falling edge BCLK rising time (10 pF load) BCLK falling time (10 pF load) BCLK duty cycle (normal and USB mode)
10 10 10 10 45:55:00
55:45:00
BCLK
tDL
PBLRC/ RECLRC PBDAT
tDST
tDHT
tDDA
RECDAT
Figure 5. Digital Audio Interface Master Mode Timing
Rev. 0 | Page 6 of 32
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06858-025
tDD
SSM2602
Table 7. System Clock Timing
Parameter tXTIY tMCLKDS tXTIH tXTIL tCOP tCOPDIV2 tMIN 72 40:60 32 32 20 20 Limit tMAX 60:40:00 ns ns ns ns Unit ns Description MCLK/XTI system clock cycle time MCLK/XTI duty cycle MCLK/XTI system clock pulse width high MCLK/XTI system clock pulse width low CLKOUT propagation delay from MCLK/XTI falling edge CLKODIV2 propagation delay from MCLK/XTI falling edge
tXTIH
MCLK/XTI
tCOP tXTIL tXTIY
CLKOUT
06858-035
CLKODIV2 tCOPDIV2
Figure 6. System (MCLK) Clock Timing
Rev. 0 | Page 7 of 32
SSM2602 ABSOLUTE MAXIMUM RATINGS
At 25C, unless otherwise noted. Table 8.
Parameter Supply Voltage Input Voltage Common-Mode Input Voltage Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 60 sec) Rating 5V VDD VDD -65C to +150C -40C to +85C -65C to +165C 300C
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 9. Thermal Resistance
Package Type 28-Lead, 5 mm x 5 mm LFCSP JA 28 JC 32 Unit C/W
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. 0 | Page 8 of 32
SSM2602 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
28 27 26 25 24 23 22
MCLK/XTI XTO DCVDD DGND DBVDD CLKOUT BCLK 1 2 3 4 5 6 7
PIN 1 INDICATOR
SCLK SDIN CSB MODE LLINEIN RLINEIN MICIN
SSM2602
TOP VIEW (Not to Scale)
21 20 19 18 17 16 15
MICBIAS VMID AGND AVDD ROUT LOUT PGND
PBDAT PBLRC RECDAT RECLRC HPVDD LHPOUT RHPOUT
8 9 10 11 12 13 14
Figure 7. Pin Configuration
Table 10. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Mnemonic MCLK/XTI XTO DCVDD DGND DBVDD CLKOUT BCLK PBDAT PBLRC RECDAT RECLRC HPVDD LHPOUT RHPOUT PGND LOUT ROUT AVDD AGND VMID MICBIAS MICIN RLINEIN LLINEIN MODE CSB SDIN SCLK GND Pad Type Digital Input Digital Output Digital Supply Digital Ground Digital Supply Digital Output Digital Input/Output Digital Input Digital Input/Output Digital Output Digital Input/Output Analog Supply Analog Output Analog Output Analog Ground Analog Output Analog Output Analog Supply Analog Ground Analog Output Analog Output Analog Input Analog Input Analog Input Digital Input Digital Input Digital Input/Output Digital Input Thermal Pad Description Master Clock Input/Crystal Input. Crystal Output. Digital Core Supply. Digital Ground. Digital I/O Supply. Buffered Clock Output. Digital Audio Bit Clock. DAC Digital Audio Data Input, Playback Function. DAC Sampling Rate Clock, Playback Function (from Left and Right Channels). ADC Digital Audio Data Output, Record Function. ADC Sampling Rate Clock, Record Function (from Left and Right Channels). Headphone Supply. Headphone Output for Left Channel. Headphone Output for Right Channel. Headphone Ground. Line Output for Left Channel. Line Output for Right Channel. Analog Supply. Analog Ground. Midrail Voltage Decoupling Input. Microphone Bias. Microphone Input Signal. Line Input for Right Channel. Line Input for Left Channel. Control Interface Selection to Select I2C/SPI. 3-Wire Control Interface Chip Selection, Active Low/2-Wire Control Interface I2C Address Selection. 3-Wire Control Interface Data Input/2-Wire Control Interface Data Input/Output. 3-Wire/2-Wire Control Interface Clock Input. Center Thermal Pad. Connect to PCB ground layer.
Rev. 0 | Page 9 of 32
06858-002
SSM2602 TYPICAL PERFORMANCE CHARACTERISTICS
CONVERTER FILTER RESPONSE
0 -10 -20
MAGNITUDE (dB)
0 -10 -20
-40 -50 -60 -70 -80 -90
06858-003
MAGNITUDE (dB)
-30
-30 -40 -50 -60 -70 -80 -90
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
FREQUENCY (fS)
FREQUENCY (fS)
Figure 8. ADC Digital Filter Frequency Response
Figure 10. DAC Digital Filter Frequency Response
0.05 0.04 0.03 0.02
MAGNITUDE (dB) MAGNITUDE (dB)
0.05 0.04 0.03 0.02 0.01 0 -0.01 -0.02 -0.03 -0.04
0.01 0 -0.01 -0.02 -0.03 -0.04 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
06858-004
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
FREQUENCY (fS)
FREQUENCY (fS)
Figure 9. ADC Digital Filter Ripple
Figure 11. DAC Digital Filter Ripple
Rev. 0 | Page 10 of 32
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-0.05
-0.05
06858-005
-100
-100
SSM2602
DIGITAL DE-EMPHASIS
0 -1 -2
0.4 0.3 0.2
-3
MAGNITUDE (dB)
MAGNITUDE (dB)
06858-007
-4 -5 -6 -7 -8 -9 -10 0 4 8 FREQUENCY (kHz) 12 16
0.1 0 -0.1 -0.2 -0.3 -0.4
FREQUENCY (kHz)
Figure 12. De-Emphasis Frequency Response, Audio Sampling Rate = 32 kHz
Figure 15. De-Emphasis Error, Audio Sampling Rate = 44.1 kHz
0.4 0.3 0.2
MAGNITUDE (dB)
0 -1 -2 -3 MAGNITUDE (dB) -4 -5 -6 -7 -8 -9
06858-008
0.1 0 -0.1 -0.2 -0.3 -0.4
0
4
8 FREQUENCY (kHz)
12
16
FREQUENCY (kHz)
Figure 13. De-Emphasis Error, Audio Sampling Rate = 32 kHz
Figure 16. De-Emphasis Frequency Response, Audio Sampling Rate = 48 kHz
0 -1 -2
0.4 0.3 0.2 MAGNITUDE (dB) 0.1 0 -0.1 -0.2 -0.3 -0.4
06858-009
-3
MAGNITUDE (dB)
-4 -5 -6 -7 -8 -9 -10 0 4 8 12 16 20
0
4
8
12 FREQUENCY (kHz)
16
20
24
FREQUENCY (kHz)
Figure 14. De-Emphasis Frequency Response, Audio Sampling Rate = 44.1 kHz
Figure 17. De-Emphasis Error, Audio Sampling Rate = 48 kHz
Rev. 0 | Page 11 of 32
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06858-011
-10
0
4
8
12
16
20
24
06858-010
0
4
8
12
16
20
SSM2602 THEORY OF OPERATION
DIGITAL CORE
Inside the SSM2602 digital core is one central clock source, called the master clock (MCLK), that produces a reference clock for all internal audio data processing and synchronization. When using an external clock source to drive the MCLK pin, great care should be taken to select a clock source with less than 50 ps of jitter. Without careful generation of the MCLK signal, the digital audio quality will most likely suffer. To enable the SSM2602 to generate the central reference clock in a system, connect a crystal oscillator between the MCLK/XTI input pin and the XTO output pin. To allow an external device to generate the central reference clock, apply the external clock signal directly through the MCLK/XTI input pin. In this configuration, the oscillator circuit of the SSM2602 can be powered down by using the OSC bit (Register R6, Bit D5) to reduce power consumption. To accommodate applications with very high frequency master clocks, the internal core reference clock of the SSM2602 can be set to either MCLK or MCLK divided by 2. This is enabled by adjusting the setting of the CLKDIV2 bit (Register R8, Bit D6). Complementary to this feature, the CLKOUT pin can also drive external clock sources with either the core clock signal or core clock divided by 2 by enabling the CLKODIV2 bit (Register R8, Bit D7). must choose either the line inputs or the microphone input as the source using the INSEL bit (Register R4, Bit D2). The digital data from the ADC output, once converted, is processed using the ADC filters. Complementary to the ADC channels, the SSM2602 contains a pair of oversampling - DACs that convert the digital audio data from the internal DAC filters into an analog audio signal. The DAC output can also be muted by setting the DACMU bit (Register R5, Bit D3) in the control register.
ADC HIGH-PASS AND DAC DE-EMPHASIS FILTERS
The ADC and DAC employ separate digital filters that perform 24-bit signal processing. The digital filters are used for both record and playback modes and are optimized for each individual sampling rate used. For recording mode operations, the unprocessed data from the ADC enters the ADC filters and is converted to the appropriate sampling frequency, and then is output to the digital audio interface. For playback mode operations, the DAC filters convert the digital audio interface data to oversampled data, using a sampling rate selected by the user. The oversampled data is processed by the DAC and then is sent to the analog output mixer by enabling the DACSEL (Register R4, Bit D4). Users have the option of setting up the device so that any dc offset in the input source signal is automatically detected and removed. To accomplish this, enable the digital high-pass filter (see Table 2 for characteristics) contained in the ADC digital filters by using the ADCHPF bit (Register R5, Bit D0). In addition, users can implement digital de-emphasis by using the DEEMPH bits (Register R5, Bit D1 and Bit D2).
ADC AND DAC
The SSM2602 contains a pair of oversampling - ADCs. The maximum ADC full-scale input level is 1.0 V rms when AVDD = 3.3 V. If the input signal to the ADC exceeds this level, data overloading occurs and causes audible distortion. The ADC can accept analog audio input from either the stereo line inputs or the monaural microphone input. Note that the ADC can only accept input from a single source, so the user
Rev. 0 | Page 12 of 32
SSM2602
AUTOMATIC LEVEL CONTROL (ALC)
The SSM2602 codec has an automatic level control (ALC) that can be activated to suppress clipping and improve dynamic range even if a sudden, loud input signal is introduced. This is achieved by continuously adjusting the PGA gain so that the signal level at the ADC input remains constant. return to its target value, therefore, depends on both the attack time and the gain adjustment required. If the gain adjustment is small, the time to return to the target value will be less than the attack time.
Noise Gate
When the ALC function is enabled but the input signal is silent for long periods, an audible hissing sound may be introduced by a phenomenon called noise pumping. To prevent this occurrence, the SSM2602 employs a noise gate function. A user-selected threshold can be set by using the NGTH bits (Register R18, Bit D3 to Bit D7). When the noise gate is enabled, the ADC output is either muted or held at a constant gain to prevent the noise-pumping phenomenon. For more information about the noise gate settings, see Table 42.
Decay (Gain Ramp-Up) Time
Decay time is the time taken for the PGA gain to ramp up to 90% of its range. The time for the recording level to return to its target value, therefore, depends on both the decay time and the gain adjustment required. If the gain adjustment is small, the time to return to the target value will be less than the decay time.
Attack (Gain Ramp-Down) Time
Attack time is the time taken for the PGA gain to ramp down through 90% of its range. The time for the recording level to
INPUT SIGNAL
PGA
SIGNAL AFTER ALC
ALC TARGET VALUE
DECAY TIME
ATTACK TIME
Figure 18. PGA and ALC Decay Time and Attack Time Definitions
Rev. 0 | Page 13 of 32
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SSM2602
ANALOG INTERFACE
Signal Chain
The SSM2602 includes stereo single-ended line and monaural microphone inputs to the on-board ADC. Either the line inputs or the microphone input, but not both simultaneously, can be connected to the ADC by setting the INSEL bit (Register R4, Bit D2). In addition, the line or microphone inputs can be routed and mixed directly to the output terminals via the SIDETONE_EN (Register R4, Bit D5) and BYPASS (Register R4, Bit D3) bits. The SSM2602 also includes line and headphone outputs from the on-board DAC.
GAIN = 50k (REXT + 10k) REXT MICIN 10k 50k
0/20dB/40dB GAIN BOOST
AVDD
VMID
ADC OR SIDETONE
Stereo Line and Monaural Microphone Inputs
The SSM2602 contains a set of single-ended stereo line inputs (RLINEIN and LLINEIN) that are internally biased to VMID by way of a voltage divider between AVDD and AGND. The line input signal can be connected to the internal ADC and, if desired, routed directly to the outputs via the bypass path by using the BYPASS bit (Register R4, Bit D3).
LINEIN
AGND
INTERNAL CIRCUITRY
Figure 20. Microphone Input to ADC
The first gain stage is composed of a low noise operational amplifier set to an inverting configuration with integrated 50 k feedback and 10 k input resistors. The default microphone input signal gain is 14 dB. An external resistor (REXT) can be connected in series with the MICIN pin to reduce the first-stage gain of the microphone input signal to as low as 0 dB by using the following equation: Microphone Input Gain = 50 k/(10 k + REXT) The second-stage gain of the microphone signal path is derived from the internal microphone boost circuitry. The available settings are 0 dB, 20 dB, and 40 dB and are controlled by the MICBOOST (Register R4, Bit D0) and MICBOOST2 (Register R4, Bit D8) bits. To achieve 20 dB of secondary gain boost, the user can select either MICBOOST or MICBOOST2. To achieve 40 dB of secondary microphone signal gain, the user must select both MICBOOST and MICBOOST2. In similar functionality to the line inputs, the user can set the MUTEMIC bit (Register R4, Bit D1) to mute the microphone input signal to the ADC. Note that when sourcing audio data from both line and microphone inputs, the maximum full-scale input of the ADC is 1.0 V rms when AVDD = 3.3 V. Do not source any input voltage larger than full scale to avoid overloading the ADC, which causes distortion of sound and deterioration of audio quality. For best sound quality in both microphone and line inputs, gain should be carefully configured so that the ADC receives a signal equal to its full scale. This maximizes the signal-to-noise ratio for best total audio quality.
AVDD
- VMID +
ADC OR BYPASS
AGND
Figure 19. Line Input to ADC
The line input volume can be adjusted from -34.5 dB to +33 dB in steps of +1.5 dB by setting the LINVOL (Register R0, Bit D0 to Bit D5) and RINVOL (Register R1, Bit D0 to Bit D5) bits. Volume control, by default, is independently adjustable on both right and left line inputs. However, the LRINBOTH or RLINBOTH bit, if selected, simultaneously loads both sets of volume control with the same value. The user can also set the LINMUTE (Register R0, Bit D7) and RINMUTE (Register R1, Bit D7) bits to mute the line input signal to the ADC. The high impedance, low capacitance monaural microphone input pin (MICIN) has two gain stages and a microphone bias level (MICBIAS) that is internally biased to the VMID voltage level by way of a voltage divider between AVDD and AGND. The microphone input signal can be connected to the internal ADC and, if desired, routed directly to the outputs via the sidetone path by using the SIDETONE_EN bit (Register R4, Bit D5).
06858-031
Rev. 0 | Page 14 of 32
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SSM2602
Bypass and Sidetone Paths to Output
The line and microphone inputs can be routed and mixed directly to the output terminals via the SIDETONE_EN (Register R4, Bit D5) and BYPASS (Register R4, Bit D3) software control register selections. In both of these modes, the analog input signal is routed directly to the output terminals and is not digitally converted. The bypass signal at the output mixer is the same level as the output of the PGA associated with each line input. The sidetone signal at the output mixer must be attenuated by a range of -6 dB to -15 dB in steps of -3 dB by configuring the SIDETONE_ATT (Register R4, Bit D6 and Bit D7) control register bits. The selected level of attenuation occurs after the initial microphone signal amplification from the microphone first- and second-stage gains. The SSM2602 has a set of efficient headphone amplifier outputs, LHPOUT and RHPOUT, that are able to drive 16 or 32 headphone speakers.
DAC/ SIDETONE/ BYPASS AVDD
- VMID + xHPOUT
AGND
Figure 22. Headphone Output
Line and Headphone Outputs
The DAC outputs, the microphone (the sidetone path), and the line inputs (the bypass path) are summed at an output mixer. This output signal can be present at both the stereo line outputs and stereo headphone outputs.
BYPASS LINE INPUT
In similar functionality to the line inputs, the LHPOUT and RHPOUT volumes, by default, are independently adjusted by setting the LHPVOL (Register R2, Bit D0 to Bit D6) and RHPVOL (Register R3, Bit D0 to Bit D6) bits of the headphone output control registers. The headphone outputs can be muted by writing codes less than 0110000 to the LHPVOL and RHPVOL bits. The user is also able to simultaneously load the volume control of both channels by writing to the LRHPBOTH (Register R2, Bit D8) and RLHPBOTH (Register R3, Bit D8) bits of the left- and rightchannel DAC volume registers. The maximum output level of the headphone outputs is 1.0 V rms when AVDD and HPVDD = 3.3 V. To suppress audible pops and clicks, the headphone and line outputs are held at the VMID dc voltage level when the device is set to standby mode or in the event that the headphone outputs are muted. The stereo line outputs of the SSM2602, the LOUT and ROUT pins, are able to drive a load impedance of 10 k and 50 pF. The line output signal levels are not adjustable at the output mixer, having a fixed gain of 0 dB. The maximum output level of the line outputs is 1.0 V rms when AVDD = 3.3 V.
SIDETONE MICROPHONE INPUT
DACSEL DAC OUTPUT LINE OUTPUT AND HEADPHONE OUTPUT
AVDD
VMID
06858-033
AGND
Figure 21. Output Signal Chain
Rev. 0 | Page 15 of 32
06858-034
SSM2602
DIGITAL AUDIO INTERFACE
The digital audio input can support the following four digital audio communication protocols: right-justified mode, left-justified mode, I2S mode, and digital-signal processor (DSP) mode. The mode selection is performed by writing to the FORMAT bits of the digital audio interface register (Register R7, Bit D1 and Bit D0). All modes are MSB first and operate with data of 16 to 32 bits.
Digital Audio Data Sampling Rate
To accommodate a wide variety of commonly used DAC and ADC sampling rates, the SSM2602 allows for two modes of operation, normal and USB, selected by the USB bit (Register R8, Bit D0). In normal mode, the SSM2602 supports digital audio sampling rates from 8 kHz to 96 kHz. Normal mode supports 256 fS and 384 fS based clocks. To select the desired sampling rate, the user must set the appropriate sampling rate register in the SR control bits (Register R8, Bit D2 to Bit D5) and match this selection to the core clock frequency that is pulsed on the MCLK pin. See Table 30 and Table 31 for guidelines. In USB mode, the SSM2602 supports digital audio sampling rates from 8 kHz to 96 kHz. USB mode is enabled on the SSM2602 to support the common universal serial bus (USB) clock rate of 12 MHz, or to support 24 MHz if the CLKDIV2 control register bit is activated. The user must set the appropriate sampling rate in the SR control bits (Register R8, Bit D2 to Bit D5). See Table 30 and Table 31 for guidelines. Note that the sampling rate is generated as a fixed divider from the MCLK signal. Because all audio processing references the core MCLK signal, corruption of this signal, in turn, corrupts the outgoing audio quality of the SSM2602. The BCLK/RECLRC/ RECDAT or BCLK/PBLRC/PBDAT signals must be synchronized with MCLK in the digital audio interface circuit. MCLK must be faster or equal to the BCLK frequency to guarantee that no data is lost during data synchronization. The BCLK frequency should be greater than Sampling Rate x Word Length x 2 Ensuring that the BCLK frequency is greater than this value guarantees that all valid data bits are captured by the digital audio interface circuitry. For example, if a 32 kHz digital audio sampling rate with a 32-bit word length is desired, BCLK 2.048 MHz.
Recording Mode
On the RECDAT output pin, the digital audio interface can send digital audio data for recording mode operation. The digital audio interface outputs the processed internal ADC digital filter data onto the RECDAT output. The digital audio data stream on RECDAT comprises left- and right-channel audio data that is time domain multiplexed. The RECLRC is the digital audio frame clock signal that separates left- and right-channel data on the RECDAT lines. The BCLK signal acts as the digital audio clock. Depending on if the SSM2602 is in master or slave mode, the BCLK signal is either an input or an output signal. During a recording operation, RECDAT and RECLRC must be synchronous to the BCLK signal to avoid data corruption.
Playback Mode
On the PBDAT input pin, the digital audio interface can receive digital audio data for playback mode operation. The digital audio data stream on PBDAT comprises left- and right-channel audio data that is time domain multiplexed. The PBLRC is the digital audio frame clock signal that separates left- and right-channel data on the PBDAT lines. The BCLK signal acts as the digital audio clock. Depending on if the SSM2602 is in master or slave mode, the BCLK signal is either an input or an output signal. During a playback operation, PBDAT and PBLRC must be synchronous to the BCLK signal to avoid data corruption.
1/fS LEFT CHANNEL RECLRC/ PBLRC RIGHT CHANNEL
BCLK
RECDAT/ PBDAT X = DON'T CARE.
1
2
3
4
N
X
X
1
2
3
N
X
X
06858-013
Figure 23. Left-Justified Audio Input Mode
Rev. 0 | Page 16 of 32
SSM2602
1/fS LEFT CHANNEL RECLRC/ PBLRC RIGHT CHANNEL
BCLK
RECDAT/ PBDAT
X
X
N
4
3
2
1
X
X
N
4
3
2
1
06858-014
X = DON'T CARE.
Figure 24. Right-Justified Audio Input Mode
1/fS LEFT CHANNEL RIGHT CHANNEL
RECLRC/ PBLRC
BCLK
RECDAT/ PBDAT
X
1
2
3
4
N
X
X
1
2
3
N
X
X = DON'T CARE.
Figure 25. I2S Audio Input Mode
1/fS LEFT CHANNEL RECLRC/ PBLRC RIGHT CHANNEL
BCLK
RECDAT/ PBDAT X = DON'T CARE.
1
2
3
N
1
2
3
N
X
X
X
06858-016
Figure 26. DSP/Pulse Code Modulation (PCM) Mode Audio Input Submode 1 (SM1) [Bit LRP = 0]
1/fS LEFT CHANNEL RECLRC/ PBLRC RIGHT CHANNEL
BCLK
RECDAT/ PBDAT X = DON'T CARE.
X
1
2
3
N
1
2
3
N
X
X
06858-017
Figure 27. DSP/PCM Mode Audio Input Submode 2 (SM2) [Bit LRP = 1]
Rev. 0 | Page 17 of 32
06858-015
SSM2602
SOFTWARE CONTROL INTERFACE
The software control interface provides access to the user-selectable control registers and can operate with a 2-wire (I2C) or 3-wire (SPI) interface, depending on the setting of the MODE pin. If the MODE pin is set to 0, the 2-wire interface is selected; if 1, the 3-wire interface is selected. Within each control register is a control data-word consisting of 16 bits, MSB first. Bit B15 to Bit B9 are the register map address, and Bit B8 to Bit B0 are register data for the associated register map.
CSB
When 2-wire (I2C) mode is selected, SDIN generates the serial control data-word, SCLK clocks the serial data, and CSB determines the I2C device address. If the CSB pin is set to 0, the address selected is 0011010; if 1, the address is 0011011. When 3-wire (SPI) mode is selected, SDIN generates the control data-word, SCLK clocks the control data-word into the SSM2602, and CSB latches in the control data-word.
SCLK
SDIN
B15
B14
B13
B12
B11
B10
B09
B08
B07
B06
B05
B04
B03
B02
B01
B0
06858-018
REGISTER MAP ADDRESS
REGISTER DATA
Figure 28. SPI Serial Interface
SDIN
SCLK
S START
1-7 ADDR
8 R/W
9 ACK
1-7
8
9 ACK
1-7 DATA
8
9 ACK
P STOP
SUBADDRESS
Figure 29. SSM2602 2-Wire I2C Generalized Clocking Diagram
WRITE SEQUENCE
S
A7
...
A1
A0 0
A(S)
B15 ...
B9
B8
A(S)
B7
...
B0
A(S)
P
DEVICE ADDRESS READ SEQUENCE
REGISTER ADDRESS
REGISTER DATA
S
A7
...
A1
A0 0
A(S)
B15
...
B9
0
A(S)
S
A7
...
A1
A0 1
A(S)
B7
...
B0
A(M)
0
06858-019
...
0
B8
A(M)
P
DEVICE ADDRESS
REGISTER ADDRESS
DEVICE ADDRESS
REGISTER DATA (SLAVE DRIVE)
Figure 30. SSM2602 I2C Write and Read Sequences
Rev. 0 | Page 18 of 32
06858-022
S/P = START/STOP BIT. A0 = I2C R/W BIT. A(S) = ACKNOWLEDGE BY SLAVE. A(M) = ACKNOWLEDGE BY MASTER. A(M) = ACKNOWLEDGE BY MASTER (INVERSION).
SSM2602 TYPICAL APPLICATION CIRCUITS
AVDD VMID AGND DBVDD DGND DCVDD HPVDD PGND REF PWROFF MICBIAS ADC RLINEIN MUX ADC
SSM2602
BYPASS SIDETONE DAC DAC
RHPOUT
ROUT MICIN MIC LLINEIN LINE SIDETONE BYPASS OSC OSC CLKOUT CLK GEN DIGITAL AUDIO INTERFACE CONTROL INTERFACE MUX ADC DAC LHPOUT DIGITAL PROCESSOR OUT LOUT
MCLK/XTI
XTO
CLKOUT
PBDAT RECDAT BCLK PBLRC RECLRC MODE CSB
SDIN SCLK
Figure 31. SSM2602 Power Management Functional Location Diagram (Control Register R6, Bit D0 to Bit D7)
+3.3V_VAA
L2 FB
L1 FB C23 0.1uF
C20 0.1uF
C21 10uF +
+
C22 10uF
+3,3V_VDD C18 10uF
+
18 12
C19 0.1uF C24 0.1uF
5
U1
AVDD
J1 1
HPVDD
DBVDD
R2
C2 1uF C4 220PF 1uF 23 24 L_LINE_IN ROUT 17
DCVDD
R1 0
C1
3
+
C25 10uF
06858-020
NC L
C12 1uF
J4 R11 100 J5 BNC 1 BNC
2
+
J2 1
R3 0 21 R4 NC C5 220PF
R_LINE_IN
LOUT
16 C14
+
1 R12 100 R9 47K R10 47K
MIC_BIAS
LHP_OUT
13
+
2
C15 22 I2S[0..4] DACLRC DACDAT ADCDAT ADCLRC BCLK 9 8 10 11 7 PBLRC PBDAT RECDAT RECLRC BCLK MIC_IN RHP_OUT SSM2602KCPZ 14
R
220uF J6 C27 220PF CLKOUT 6 R14 47K C26 R13 47K 1 2 3 4 5
+3.3V_VAA
J7 MIC_IN 1
R7 680 C10 R8
R5 100K
R6 NC CSB SDIN SCLK
25 26 27 28
2
MODE CSB SDIN SCLK
+
220uF
VMID
20
220PF PHONEJACK STEREO SW
R15 47K C11 220PF
SPI[0..2] 1uF 0 Y1 1 MCLK/XTI
C6 0.1uF
+
C3 10uF
AVSS HPVSS
2 12.288MHz C7 22pF C8 22pF
19 15
Figure 32. SSM2602 Typical Application Circuit
Rev. 0 | Page 19 of 32
06858-023
Connection under chip
4
DVSS
POR/XTO
2
C13 1uF
2
SSM2602 REGISTER MAP
Table 11. Register Map
Reg. Address Name D8 R0 0x00 Left-Channel LRINBOTH ADC Input Volume R1 R2 R3 R4 R5 R6 R7 R8 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 Right-Channel ADC Input Volume Left-Channel DAC Volume Right-Channel DAC Volume Analog Audio Path Digital Audio Path Power Management Digital Audio I/F Sampling Rate Active Software Reset ALC Control 1 ALC Control 2 Noise Gate RLINBOTH LRHPBOTH RLHPBOTH MICBOOST2 0 0 0 0 0 0 PWROFF BCLKINV D7 LINMUTE RINMUTE LZCEN RZCEN SIDETONE_ATT [1:0] 0 CLKOUT MS D6 0 0 D5 D4 D3 D2 LINVOL [5:0] RINVOL [5:0] LHPVOL [6:0] RHPVOL [6:0] SIDETONE_EN DACSEL BYPASS 0 OSC LRSWAP HPOR OUT LRP SR [3:0] 0 0 RESET [8:0] 0 0 DACMU DAC INSEL D1 D0 Default 010010111 010010111 001111001 001111001 MUTEMIC MICBOOST 000001010 ADCHPF LINEIN FORMAT [1:0] BOSR 0 USB ACTIVE 000001000 010011111 000001010 000000000 000000000 000000000 001111011 000110010 NGAT 000000000
DEEMPH [1:0] ADC MIC
WL [1:0]
CLKODIV2 CLKDIV2 0 0
R9 0x09 R15 0x0F R16 0x10 R17 0x11 R18 0x12
ALCSEL [1:0] 0 0
MAXGAIN [2:0] DCY [3:0] NGTH [4:0]
ALCL [3:0] ATK [3:0] NGG [1:0]
Rev. 0 | Page 20 of 32
SSM2602 REGISTER MAP DETAILS
LEFT-CHANNEL ADC INPUT VOLUME, ADDRESS 0x00
Table 12. Left-Channel ADC Input Volume Register Bit Map
D8 LRINBOTH D7 LINMUTE D6 0 D5 D4 D3 D2 LINVOL [5:0] D1 D0
Table 13. Descriptions of Left-Channel ADC Input Volume Register Bits
Bit Name LRINBOTH Description Left-to-right line input ADC data load control Settings 0 = disable simultaneous loading of left-channel ADC data to rightchannel register (default) 1 = enable simultaneous loading of left-channel ADC data to rightchannel register 0 = disable mute 1 = enable mute on data path to ADC (default) 00 0000 = -34.5 dB ... 1.5 dB step up 01 0111 = 0 dB (default) ... 1.5 dB step up 01 1111 = 12 dB 10 0000 = 13.5 dB 10 0001 = 15 dB 10 0010 = 16.5 dB 10 0011 = 18 dB 10 0100 = 19.5 dB 10 0101 = 21 dB 10 0110 = 22.5 dB 10 0111 = 24 dB 10 1000 = 25.5 dB 10 1001 = 27 dB 10 1010 = 28.5 dB 10 1011 = 30 dB 10 1100 = 31.5 dB 10 1101 = 33 dB 11 1111 to 10 1101 = 33 dB
LINMUTE LINVOL [5:0]
Left-channel input mute Left-channel PGA volume control
Rev. 0 | Page 21 of 32
SSM2602
RIGHT-CHANNEL ADC INPUT VOLUME, ADDRESS 0x01
Table 14. Right-Channel ADC Input Volume Register Bit Map
D8 RLINBOTH D7 RINMUTE D6 0 D5 D4 D3 D2 RINVOL [5:0] D1 D0
Table 15. Descriptions of Right-Channel ADC Input Volume Register Bits
Bit Name RLINBOTH Description Right-to-left line input ADC data load control Settings 0 = disable simultaneous loading of right-channel ADC data to leftchannel register (default) 1 = enable simultaneous loading of right-channel ADC data to leftchannel register 0 = disable mute 1 = enable mute on data path to ADC (default) 00 0000 = -34.5 dB ... 1.5 dB step up 01 0111 = 0 dB (default) ... 1.5 dB step up 01 1111 = 12 dB 10 0000 = 13.5 dB 10 0001 = 15 dB 10 0010 = 16.5 dB 10 0011 = 18 dB 10 0100 = 19.5 dB 10 0101 = 21 dB 10 0110 = 22.5 dB 10 0111 = 24 dB 10 1000 = 25.5 dB 10 1001 = 27 dB 10 1010 = 28.5 dB 10 1011 = 30 dB 10 1100 = 31.5 dB 10 1101 = 33 dB 11 1111 to 10 1101 = 33 dB
RINMUTE RINVOL [5:0]
Right-channel input mute Right-channel PGA volume control
Rev. 0 | Page 22 of 32
SSM2602
LEFT-CHANNEL DAC VOLUME, ADDRESS 0x02
Table 16. Left-Channel DAC Volume Register Bit Map
D8 LRHPBOTH D7 LZCEN D6 D5 D4 D3 D2 LHPVOL [6:0] D1 D0
Table 17. Descriptions of Left-Channel DAC Volume Register Bits
Bit Name LRHPBOTH Description Left-to-right headphone volume load control Settings 0 = disable simultaneous loading of left-channel headphone volume data to right-channel register (default) 1 = enable simultaneous loading of left-channel headphone volume data to right-channel register 0 = disable (default) 1 = enable 000 0000 to 010 1111 = mute 011 0000 = -73 dB ... 111 1001 = 0 dB (default) ... 1 dB steps up to 111 1111 = +6 dB
LZCEN LHPVOL [6:0]
Left-channel zero cross detect enable Left-channel headphone volume control
RIGHT-CHANNEL DAC VOLUME, ADDRESS 0x03
Table 18. Right-Channel DAC Volume Register Bit Map
D8 RLHPBOTH D7 RZCEN D6 D5 D4 D3 D2 RHPVOL [6:0] D1 D0
Table 19. Descriptions of Right-Channel DAC Volume Register Bits
Bit Name RLHPBOTH Description Right-to-left headphone volume load control Settings 0 = disable simultaneous loading of right-channel headphone volume data to left-channel register (default) 1 = enable simultaneous loading of right-channel headphone volume data to left-channel register 0 = disable (default) 1 = enable 000 0000 to 010 1111 = mute 011 0000 = -73 dB ... 111 1001 = 0 dB (default) ... 1 dB steps up to 111 1111 = +6 dB
RZCEN RHPVOL [6:0]
Right-channel zero cross detect enable Right-channel headphone volume control
Rev. 0 | Page 23 of 32
SSM2602
ANALOG AUDIO PATH, ADDRESS 0x04
Table 20. Analog Audio Path Register Bit Map
D8 MICBOOST2 D7 D6 SIDETONE_ATT [1:0] D5 SIDETONE_EN D4 DACSEL D3 BYPASS D2 INSEL D1 MUTEMIC D0 MICBOOST
Table 21. Descriptions of Analog Audio Path Register Bits
Bit Name MICBOOST2 SIDETONE_ATT [1:0] Description Additional microphone amplifier gain booster control. Microphone sidetone gain control. Settings 0 = 0 dB (default) 1 = 20 dB 00 = -6 dB (default) 01 = -9 dB 10 = -12 dB 11 = -15 dB 0 = sidetone disable (default) 1 = sidetone enable 0 = do not select DAC (default) 1 = select DAC 0 = bypass disable 1 = bypass enable (default) 0 = line input select to ADC (default) 1 = microphone input select to ADC 0 = mute on data path to ADC disable 1 = mute on data path to ADC enable (default) 0 = 0 dB (default) 1 = 20 dB
SIDETONE_EN DACSEL BYPASS INSEL MUTEMIC MICBOOST
Sidetone enable. Allow attenuated microphone signal to be mixed at device output terminal. DAC select. Allow DAC output to be mixed at device output terminal. Bypass select. Allow line input signal to be mixed at device output terminal. Line input or microphone input select to ADC. Microphone mute control to ADC. Primary microphone amplifier gain booster control.
DIGITAL AUDIO PATH, ADDRESS 0x05
Table 22. Digital Audio Path Register Bit Map
D8 0 D7 0 D6 0 D5 0 D4 HPOR D3 DACMU D2 D1 DEEMPH [1:0] D0 ADCHPF
Table 23. Descriptions of Digital Audio Path Register Bits
Bit Name HPOR DACMU DEEMPH [1:0] Description Store dc offset when high-pass filter is disabled DAC digital mute De-emphasis control Settings 0 = clear offset (default) 1 = store offset 0 = no mute (signal active) 1 = mute (default) 00 = no de-emphasis (default) 01 = 32 kHz sampling rate 10 = 44.1 kHz sampling rate 11 = 48 kHz sampling rate 0 = ADC high-pass filter enable (default) 1 = ADC high-pass filter disable
ADCHPF
ADC high-pass filter control
Rev. 0 | Page 24 of 32
SSM2602
POWER MANAGEMENT, ADDRESS 0x06
Table 24. Power Management Register Bit Map
D8 0 D7 PWROFF D6 CLKOUT D5 OSC D4 OUT D3 DAC D2 ADC D1 MIC D0 LINEIN
Table 25. Description of Power Management Register Bits
Bit Name PWROFF CLKOUT OSC OUT DAC ADC MIC LINEIN Description Whole chip power-down control Clock output power-down control Crystal power-down control Output power-down control DAC power-down control ADC power-down control Microphone input power-down control Line input power-down control Settings 0 = power up 1 = power down (default) 0 = power up (default) 1 = power down 0 = power up (default) 1 = power down 0 = power up 1 = power down (default) 0 = power up 1 = power down (default) 0 = power up 1 = power down (default) 0 = power up 1 = power down (default) 0 = power up 1 = power down (default)
Power Consumption
Table 26.
Mode Record and Playback Playback Only Oscillator Enabled External Clock Record Only Line Clock Line Oscillator Microphone 1 Microphone 2 Sidetone (Microphone-toHeadphone Output) External Clock Internally Generated Clock Analog Bypass (Line Input or Line Output) External Line Internally Generated Line Power-Down External Clock Oscillator PWROFF 0 0 0 0 0 0 0 CLKOUT 0 0 1 0 0 0 0 OSC 0 0 1 0 1 0 1 OUT 0 0 0 1 1 1 1 DAC 0 0 0 1 1 1 1 ADC 0 1 1 0 0 0 0 MIC 0 1 1 1 1 0 0 LINEIN 0 1 1 0 0 1 1 AVDD (3.3V) 10.7 5.2 5.1 4.7 4.7 4.8 4.8 HPVDD (3.3 V) 2.2 2.2 2.2 N/A N/A N/A N/A DCVDD (3.3 V) 3.6 1.7 1.7 2.0 2.0 2.0 2.0 DBVDD (3.3 V) 3.1 1.8 1.7 1.9 1.8 1.9 1.8 Unit mA mA mA mA mA mA mA
0 0
0 0
1 1
0 0
1 1
1 1
0 0
1 1
2.0 2.0
2.2 2.2
0.2 0.2
1.7 1.7
mA mA
0 0
0 0
1 1
0 0
1 1
1 1
1 1
0 0
2.0 2.0
2.2 2.2
0.2 0.2
1.7 1.7
mA mA
1 1
1 1
1 1
1 1
1 1
1 1
1 1
1 1
0.001 0.001
<1uA <1uA
0.03 0.03
0.03 0.03
mA mA
Rev. 0 | Page 25 of 32
SSM2602
DIGITAL AUDIO I/F, ADDRESS 0x07
Table 27. Digital Audio I/F Register Bit Map
D8 0 D7 BCLKINV D6 MS D5 LRSWAP D4 LRP D3 D2 WL [1:0] D1 D0 FORMAT [1:0]
Table 28. Descriptions of Digital Audio I/F Register Bits
Bit Name BCLKINV MS LRSWAP LRP WL [1:0] Description BCLK inversion control Master mode enable Swap DAC data control Polarity control for clocks in right-justified, left-justified, and I2S modes Data-word length control Settings 0 = BCLK not inverted (default) 1 = BCLK inverted 0 = enable slave mode (default) 1 = enable master mode 0 = output left- and right-channel data as normal (default) 1 = swap left- and right-channel DAC data in audio interface 0 = normal PBLRC and RECLRC (default), or DSP Submode 1 1 = invert PBLRC and RECLRC polarity, or DSP Submode 2 00 = 16 bits 01 = 20 bits 10 = 24 bits (default) 11 = 32 bits 00 = right justified 01 = left justified 10 = I2S mode (default) 11 = DSP mode
FORMAT [1:0]
Digital audio input format control
SAMPLING RATE, ADDRESS 0x08
Table 29. Sampling Rate Register Bit Map
D8 0 D7 CLKODIV2 D6 CLKDIV2 D5 D4 D3 SR [3:0] D2 D1 BOSR D0 USB
Table 30. Descriptions of Sampling Rate Register Bits
Bit Name CLKODIV2 CLKDIV2 SR [3:0] BOSR Description CLKOUT divider select Core clock divide select Clock setting condition Base oversampling rate Settings 0 = CLKOUT is core clock (default) 1 = CLKOUT is core clock divided by 2 0 = core clock is MCLK (default) 1= core clock is MCLK divided by 2 See Table 31 and Table 32. USB mode: 0 = support for 250 fS based clock (default) 1 = support for 272 fS based clock Normal mode: 0 = support for 256 fS based clock (default) 1 = support for 384 fS based clock 0 = normal mode enable (default) 1 = USB mode enable
USB
USB mode select
Rev. 0 | Page 26 of 32
SSM2602
Table 31. Sampling Rate Lookup Table, USB Disabled (Normal Mode)
MCLK (CLKDIV2 = 0) 12.288 MHz MCLK (CLKDIV2 = 1) 24.576 MHz ADC Sampling Rate (RECLRC) 8 kHz (MCLK/1536) 8 kHz (MCLK/1536) 12 kHz (MCLK/1024) 16 kHz (MCLK/768) 24 kHz (MCLK/512) 32 kHz (MCLK/384) 48 kHz (MCLK/256) 48 kHz (MCLK/256) 96 kHz (MCLK/128) 8.0182 kHz (MCLK/1408) 8.0182 kHz (MCLK/1408) 11.025 kHz (MCLK/1024) 22.05 kHz (MCLK/512) 44.1 kHz (MCLK/256) 44.1 kHz (MCLK/256) 88.2 kHz (MCLK/128) 8 kHz (MCLK/2304) 8 kHz (MCLK/2304) 12 kHz (MCLK/1536) 16 kHz (MCLK/1152) 24 kHz (MCLK/768) 32 kHz (MCLK/576) 48 kHz (MCLK/384) 48 kHz (MCLK/384) 96 kHz (MCLK/192) 8.0182 kHz (MCLK/2112) 8.0182 kHz (MCLK/2112) 11.025 kHz (MCLK/1536) 22.05 kHz (MCLK/768) 44.1 kHz (MCLK/384) 44.1 kHz (MCLK/384) 88.2 kHz (MCLK/192)
1
11.2896 MHz
22.5792 MHz
18.432 MHz
36.864 MHz
16.9344 MHz
33.8688 MHz
DAC Sampling Rate (PBLRC) 8 kHz (MCLK/1536) 48 kHz (MCLK/256) 12 kHz (MCLK/1024) 16 kHz (MCLK/768) 24 kHz (MCLK/512) 32 kHz (MCLK/384) 8 kHz (MCLK/1536) 48 kHz (MCLK/256) 96 kHz (MCLK/128) 8.0182 kHz (MCLK/1408) 44.1 kHz (MCLK/256) 11.025 kHz (MCLK/1024) 22.05 kHz (MCLK/512) 8.0182 kHz (MCLK/1408) 44.1 kHz (MCLK/256) 88.2 kHz (MCLK/128) 8 kHz (MCLK/2304) 48 kHz (MCLK/384) 12 kHz (MCLK/1536) 16 kHz (MCLK/1152) 24 kHz (MCLK/768) 32 kHz (MCLK/576) 48 kHz (MCLK/384) 8 kHz (MCLK/2304) 96 kHz (MCLK/192) 8.0182 kHz (MCLK/2112) 44.1 kHz (MCLK/384) 11.025 kHz (MCLK/1536) 22.05 kHz (MCLK/768) 8.0182 kHz (MCLK/2112) 44.1 kHz (MCLK/384) 88.2 kHz (MCLK/192)
USB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SR [3:0] 0011 0010 0100 0101 1110 0110 0001 0000 0111 1011 1010 1100 1101 1001 1000 1111 0011 0010 0100 0101 1110 0110 0000 0001 0111 1011 1010 1100 1101 1001 1000 1111
BOSR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
BCLK (MS = 1) 1 MCLK/4 MCLK/4 MCLK/4 MCLK/4 MCLK/4 MCLK/4 MCLK/4 MCLK/4 MCLK/2 MCLK/4 MCLK/4 MCLK/4 MCLK/4 MCLK/4 MCLK/4 MCLK/2 MCLK/6 MCLK/6 MCLK/6 MCLK/6 MCLK/6 MCLK/6 MCLK/6 MCLK/6 MCLK/3 MCLK/6 MCLK/6 MCLK/6 MCLK/6 MCLK/6 MCLK/6 MCLK/3
BCLK frequency is for master mode and slave right-justified mode only.
Rev. 0 | Page 27 of 32
SSM2602
Table 32. Sampling Rate Lookup Table, USB Enabled (USB Mode)
MCLK (CLKDIV2 = 0) 12.000 MHz MCLK (CLKDIV2 = 1) 24.000 MHz ADC Sampling Rate (RECLRC) 8 kHz (MCLK/1500) 8 kHz (MCLK/1500) 8.0214 kHz (MCLK/1496) 8.0214 kHz (MCLK/1496) 11.0259 kHz (MCLK/1088) 12 kHz (MCLK/1000) 16 kHz (MCLK/750) 22.0588 kHz (MCLK/544) 24 kHz (MCLK/500) 32 kHz (MCLK/375) 44.118 kHz (MCLK/272) 44.118 kHz (MCLK/272) 48 kHz (MCLK/250) 48 kHz (MCLK/250) 88.235 kHz (MCLK/136) 96 kHz (MCLK/125) DAC Sampling Rate (PBLRC) 8 kHz (MCLK/1500) 48 kHz (MCLK/250) 8.0214 kHz (MCLK/1496) 44.118 kHz (MCLK/272) 11.0259 kHz (MCLK/1088) 12 kHz (MCLK/1000) 16 kHz (MCLK/750) 22.0588 kHz (MCLK/544) 24 kHz (MCLK/500) 32 kHz (MCLK/375) 8.0214 kHz (MCLK/1496) 44.118 kHz (MCLK/272) 8 kHz (MCLK/1500) 48 kHz (MCLK/250) 88.235 kHz (MCLK/136) 96 kHz (MCLK/125) USB 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SR [3:0] 0011 0010 1011 1010 1100 1000 1010 1101 1110 0110 1001 1000 0001 0000 1111 0111 BOSR 0 0 1 1 1 0 0 1 0 0 1 1 0 0 1 0 BCLK (MS = 1) 1 MCLK MCLK MCLK MCLK MCLK MCLK MCLK MCLK MCLK MCLK MCLK MCLK MCLK MCLK MCLK MCLK
1
BCLK frequency is for master mode and slave right-justified mode only.
Rev. 0 | Page 28 of 32
SSM2602
ACTIVE, ADDRESS 0x09
Table 33. Active Register Bit Map
D8 0 D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 D0 ACTIVE
Table 34. Descriptions of Active Register Bit
Bit Name ACTIVE Description Digital core activation control Settings 0 = disable digital core (default) 1 = activate digital core
RESET, ADDRESS 0x0F
Table 35. Software Reset Register Bit Map
D8 D7 D6 D5 D4 RESET [8:0] D3 D2 D1 D0
Table 36. Descriptions of Software Reset Register Bits
Bit Name RESET [8:0] Description Write all 0s to this register to set all registers to their default settings. Other data written to this register has no effect. Settings 0 = reset (default)
Rev. 0 | Page 29 of 32
SSM2602
ALC CONTROL 1, ADDRESS 0x10
Table 37. ALC Control 1 Register Bit Map
D8 D7 ALCSEL [1:0] D6 D5 D4 MAXGAIN [2:0] D3 D2 D1 ALCL [[3:0] D0
Table 38. Descriptions of ALC Control 1 Register Bits
Bit Name ALCSEL [1:0] Description ALC select Settings 00 = ALC disabled (default) 01 = ALC enabled on right channel only 10 = ALC enabled on left channel only 11 = ALC enabled on both channels 000 = -12 dB 001 = -6 dB ... 6 dB steps up to 111 = 30 dB (default) 0000 = -28.5 dBFS 0001 = -27 dBFS ... 1011 = -12 dBFS (default) ... 1.5 dB steps up to 1111 = -6 dBFS
MAXGAIN [2:0]
PGA maximum gain
ALCL [3:0]
ALC target level
ALC CONTROL 2, ADDRESS 0x11
Table 39. ALC Control 2 Register Bit Map
D8 0 D7 D6 D5 DCY [3:0] D4 D3 D2 D1 ATK [3:0] D0
Table 40. Descriptions of ALC Control 2 Register Bits
Bit Name DCY [3:0] Description Decay (release) time control Settings 0000 = 24 ms 0001 = 48 ms 0010 = 96 ms 0011 = 192 ms (default) ... (Time doubles with every step) 1010 = 24.576 sec 0000 = 6 ms 0001 = 12 ms 0010 = 24 ms (default) ... (Time doubles with every step) 1010 = 6.144 sec
ATK [3:0]
ALC attack time control
Rev. 0 | Page 30 of 32
SSM2602
NOISE GATE, ADDRESS 0x12
Table 41. Noise Gate Register Bit Map
D8 0 D7 D6 D5 NGTH [4:0] D4 D3 D2 D1 NGG [1:0] D0 NGAT
Table 42. Descriptions of Noise Gate Register Bits
Bit Name NGTH [4:0] Description Noise gate threshold Settings 00000 = -76.5 dBFS (default) 00001 = -75 dBFS ... 1.5 dB steps up to 11110 = -31.5 dBFS 11111 = -30 dBFS X0 = hold PGA gain constant (default) 1 01 = mute output 11 = reserved 0 = noise gate disable (default) 1 = noise gate enable
NGG [1:0]
Noise gate type
NGAT
Noise gate control
1
X = don't care.
Rev. 0 | Page 31 of 32
SSM2602 OUTLINE DIMENSIONS
5.00 BSC SQ 0.60 MAX 0.60 MAX
22
28 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
4.75 BSC SQ
0.50 BSC
21
EXPOSED PAD (BOTTOM VIEW)
15
14 8 7
3.40 3.30 SQ 3.20
0.50 0.40 0.30
0.25 MIN 3.00 REF
1.00 0.85 0.80 SEATING PLANE
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM COPLANARITY 0.05 0.20 REF
052407-B
0.30 0.23 0.18
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-1
Figure 33. 28-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm x 5 mm Body, Very Thin Quad (CP-28-4) Dimensions shown in millimeters
ORDERING GUIDE
Model SSM2602CPZ-R2 1 SSM2602CPZ-REEL1 SSM2602CPZ-REEL71 SSM2602-EVALZ1
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C
Package Description 28-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 28-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 28-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board
Package Option CP-28-4 CP-28-4 CP-28-4
Z = RoHS Compliant Part.
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06858-0-2/08(0)
Rev. 0 | Page 32 of 32

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